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Design Rule Verification Report

Date : 2014/6/13
Time : 19:21:39
Elapsed Time : 00:00:00
Filename : C:\Users\me\Desktop\DEV_Print\DEV_Print.PcbDoc
Warnings : 0
Rule Violations : 12

Summary

Warnings Count
Total 0

Rule Violations Count
Short-Circuit Constraint (Allowed=No) (All),(All) 0
Un-Routed Net Constraint ( (All) ) 0
Power Plane Connect Rule(Relief Connect )(Expansion=20mil) (Conductor Width=10mil) (Air Gap=10mil) (Entries=4) (All) 0
Width Constraint (Min=8mil) (Max=60mil) (Preferred=8mil) (All) 5
Hole Size Constraint (Min=1mil) (Max=100mil) (All) 7
Total 12

Width Constraint (Min=8mil) (Max=60mil) (Preferred=8mil) (All)
Width Constraint: Track (3490mil,2315mil)(3490mil,2505mil) TopLayer
Width Constraint: Track (3490mil,2315mil)(3595mil,2315mil) TopLayer
Width Constraint: Track (3645mil,2115mil)(3645mil,2265mil) TopLayer
Width Constraint: Track (3595mil,2315mil)(3645mil,2265mil) TopLayer
Width Constraint: Track (3310mil,2315mil)(3490mil,2315mil) TopLayer
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Hole Size Constraint (Min=1mil) (Max=100mil) (All)
Hole Size Constraint: Pad J1-3(3386mil,2115mil) MultiLayer
Hole Size Constraint: Pad J1-1(3645mil,2115mil) MultiLayer
Hole Size Constraint: Pad J1-2(3490mil,2315mil) MultiLayer
Hole Size Constraint: Pad Free-(150mil,3393.307mil) MultiLayer
Hole Size Constraint: Pad Free-(3787.008mil,3393.307mil) MultiLayer
Hole Size Constraint: Pad Free-(3787.008mil,150mil) MultiLayer
Hole Size Constraint: Pad Free-(150mil,150mil) MultiLayer
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